Balanced Mapping Space Exploration, A Mapping Tool for Manycore Processors

In this project we study the problem of mapping concurrent tasks of an application to cores of a chip multiprocessor, subject to platform constraints of various different network architectures such as regular packet-switch NoCarchitectures, circuit-switch GALS architectures, and etc. The mapping quality affects application throughput, energy consumption, and even feasibility of implementing the application. We develop a configurable algorithm that can strike a balance between mapping quality and optimization run time, during exploration of the mapping solution space. Thus, it finds application in both compile time and run time application mapping. In addition, the proposed technique can handle a number of problem requirements, such as architectural features of the target platform and various usecase scenarios (e.g., core failures), and is scalable to large number of tasks and cores.